1. Field of the Invention
The invention relates to serial link transmitters, and more particularly to data transmission of serial link transmitters.
2. Description of the Related Art
Serial link data transmission is widely used in computer systems. An example of a serial link transmission system is a serial advanced technology attachment (SATA) bus, which is a computer bus primarily designed for transfer of data between a computer and mass storage devices such as hard disk drives and optical drives. In a serial link transmission system, a serial link transmitter sequentially sends one data bit at one time over a communication channel or computer bus to a serial link receiver for data transmission. Precision and correctness of serial link data transmission is important for computer systems.
Referring to FIG. 1A, a block diagram of a serial link transmission system 100 is shown. The system 100 comprises a serial link transmitter 102 and a serial link receiver 104. The serial link transmitter 102 comprises a pair of differential transmitting terminals tx+ and tx−, and the serial link receiver 104 comprises a pair of differential receiving terminals rx+ and rx−. Two transmission lines respectively couple a positive transmitting terminal tx+ and a negative transmitting terminal tx− to a positive receiving terminal rx+ and a negative receiving terminal rx− with capacitances 112 and 114 (illustrated as equivalent capacitors). When the serial link transmitter 102 transmits data, the serial link transmitter 102 generates a pair of differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx−. Because the capacitances 112 and 114 of the transmission lines are ordinarily greater than 1 nF, only alternate current (AC) portions of the differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx− could pass through the transmission lines to be received by the serial link receiver 104.
Referring to FIG. 1B, a schematic diagram of signals received by the serial link receiver 104 of FIG. 1A is shown. Two receiving terminals rx+ and rx− of the serial link receiver 104 respectively receive signals Vrx+ and Vrx− from the transmission lines. The serial link receiver 104 comprises two resistors 122 and 124 respectively coupling the receiving terminals rx+ and rx− to a voltage source 126 with a common mode voltage Vcm—rx. During periods T1 and T13, the serial link transmitter 102 transmits no data, and both the voltages Vrx+ and Vrx− of the receiving terminals rx+ and rx− are consequently equal to the common mode voltage Vcm—rx of the voltage source 126 as shown in FIG. 1A. During a period T12, the serial link transmitter 102 transmits data through the transmission lines, and the voltages Vrx+ and Vrx− of the receiving terminals rx+ and rx− swing between threshold voltages VH—rx and VL—rx.
Referring to FIG. 2, a block diagram of a serial link transmission system 200 with a conventional serial link transmitter 202 is shown. The serial link transmitter 202 comprises a differential amplifier comprising two resistors 232 and 234 with resistance R, two differential input transistors 236 and 238, a switch 240, and a current source 242 supplying a current Iref. A negative transmitting terminal tx− is coupled to the resistor 232 and a drain of a positive input transistor 236, and a positive transmitting terminal tx+ is coupled to the resistor 234 and a drain of a negative input transistor 238. When the serial link transmitter 202 transmits data, the switch 240 couples the current source 242 to the sources of the differential input transistors 236 and 238, and the differential amplifier generates differential output signals Vtx+ and Vtx− on the transmitting terminals tx+ and tx− according to voltages Vin+ and Vin− on the gates of the differential input transistors 236 and 238. When the serial link transmitter 202 does not transmit data, the switch 240 decouples the current source 242 from the sources of the differential input transistors 236 and 238, thus disabling the differential amplifier to reduce power consumption of the serial link transmitter 202.
The circuit structure of the conventional serial link transmitter 202, however, induces abnormal initial amplitudes and abnormal initial levels of the differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx−. Referring to FIG. 3, a schematic diagram of an embodiment of voltages of transmitting terminals tx+ and tx− and receiving terminals rx+ and rx− of FIG. 2 is shown. The serial link transmitter 202 transmits no data during periods T31 and T33, and the switch 240 decouples the current source 242 from the differential amplifier 202 to disable the differential amplifier 202. Consequently, no current passes through the resistors 232 and 234, and voltages of the transmitting terminals tx+ and tx− are therefore raised to that of the voltage source VDD. At a start of the period T32, the serial link transmitter 202 starts to transmit data and generates differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx−. The transmission lines coupling the transmitting terminals tx+ and tx− and the receiving terminals rx+ and rx−, however, have capacitances 212 and 214 and require time to be gradually charged to the common mode voltage Vcm—tx. As shown in FIG. 3, before the voltages of the transmission lines reaches a steady level of the common mode voltage Vcm—tx, the differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx− have an average level deviating from the common mode voltage Vcm—tx and an oscillating amplitude smaller than a normal amplitude of (VH—tx−VL—tx).
The abnormal initial oscillating amplitude of the differential output voltages Vtx+ and Vtx− on the transmitting terminals tx+ and tx− during the signaling period T32 induces an abnormal initial oscillating amplitude of voltages Vrx+ and Vrx− on the receiving terminals rx+ and rx−. Referring to FIG. 3, during the signaling period T32, the voltages Vrx+ and Vrx− on the receiving terminals rx+ and rx− have an initial oscillating amplitude smaller than a normal amplitude of (VH—rx−VL—rx), inducing a reduced initial amplitude of a differential received signal between the voltages Vrx+ and Vrx−. If a serial link receiver, such as a SATA receiver, measures an initial amplitude of a received signal to obtain a reference for out-of-band (OOB) determination, the reduced initial amplitude of the received signal will cause errors in out-of-band determination, degrading performance of the serial link transmission system 200. Thus, a serial link transmitter generating signals with acceptable initial oscillating amplitude is required.